Address: 127.127.5.u
Reference ID: GPS, OMEGA, GOES
Driver ID: TRUETIME
Serial Port: /dev/trueu; 9600 baud, 8-bits,
no parity
Features: tty_clk
This driver supports several models models of Kinemetrics/TrueTime timing receivers, including 468-DC MK III GOES Synchronized Clock, GPS- DC MK III and GPS/TM-TMD GPS Synchronized Clock, XL-DC (a 151-602-210, reported by the driver as a GPS/TM-TMD), GPS-800 TCU (an 805-957 with the RS232 Talker/Listener module), OM-DC OMEGA Syncrhonized Clock, and very likely others in the same model family that use the same timecode formats.
Most of this code is originally from refclock_wwvb.c with thanks. It has been so mangled that wwvb is not a recognizable ancestor.
Timcode format: ADDD:HH:MM:SSQCL
A - control A (this is stripped before we see it)
Q - Quality indication (see below)
C - Carriage return
L - Line feed
Quality codes indicate possible error of
468-DC GOES Receiver:
GPS-TM/TMD Receiver:
? +/- 500 milliseconds # +/- 50 milliseconds
* +/- 5 milliseconds . +/- 1 millisecond
space less than 1 millisecond
OM-DC OMEGA Receiver:
> +/- 5 seconds
? +/- 500 milliseconds # +/- 50 milliseconds
* +/- 5 milliseconds . +/- 1 millisecond
A-H less than 1 millisecond. Character indicates which station
is being received as follows: A = Norway, B = Liberia,
C = Hawaii, D = North Dakota, E = La Reunion, F = Argentina,
G = Australia, H = Japan.
The carriage return start bit begins on 0 seconds and extends to 1 bit time.
Notes on 468-DC and OMEGA receiver:
Send the clock a R or C and once per second
a timestamp will appear. Send a R to get the satellite
position once (GOES only).
Notes on the 468-DC receiver:
Since the old east/west satellite locations are only historical, you can't set your clock propagation delay settings correctly and still use automatic mode. The manual says to use a compromise when setting the switches. This results in significant errors. The solution; use fudge time1 and time2 to incorporate corrections. If your clock is set for 50 and it should be 58 for using the west and 46 for using the east, use the line
fudge 127.127.5.0 time1 +0.008 time2 -0.004
This corrects the 4 milliseconds advance and 8 milliseconds retard needed. The software will ask the clock which satellite it sees.
The PCL720 from PC Labs has an Intel 8253 lookalike, as well as a bunch of TTL input and output pins, all brought out to the back panel. If you wire a PPS signal (such as the TTL PPS coming out of a GOES or other Kinemetrics/Truetime clock) to the 8253's GATE0, and then also wire the 8253's OUT0 to the PCL720's INPUT3.BIT0, then we can read CTR0 to get the number of microseconds since the last PPS upward edge, mediated by reading OUT0 to find out if the counter has wrapped around (this happens if more than 65535us (65ms) elapses between the PPS event and our being called.)
When enabled by the flag4 fudge flag, every received
timecode is written as-is to the clockstats file.
time1 time
time2 time
stratum number
refid string
TRUE.
flag1 0 | 1
flag2 0 | 1
flag3 0 | 1
ppsclock streams module if set.
flag4 0 | 1
clockstats recording if set.